Physics Engineering Semiconductor Technologies

[Merzifonlu]

Off topic but I found the way to build a transistor free logic gate.

In my method they are not located inside the logic gates, but are needed to build the buffers located outside the logic gates.

 

[TheInsider]

Off topic but I found the way to build a transistor free logic gate.

In my method they are not located inside the logic gates, but are needed to build the buffers located outside the logic gates.

You are wasted here bro go apply for the Nobel Prize.

 

[Merzifonlu]

You are wasted here bro go apply for the Nobel Prize.

Nope. All I need is to start a company and find venture capital. By the way, I am serious, you really don't need a transistor inside the logic gate.

All logic gates can be obtained by combining one of two universal gates. NAND or NOR logic gates. In traditional industry, NAND gate is preferred because it has 1 less transistor than NOR gate.

In my method NOR gate is more convenient because it has no transistors inside. But transistors are still needed in buffers outside of the logic gates, in my method.

 

[uçuyorum]

Nope. All I need is to start a company and find venture capital. By the way, I am serious, you really don't need a transistor inside the logic gate.

All logic gates can be obtained by combining one of two universal gates. NAND or NOR logic gates. In traditional industry, NAND gate is preferred because it has 1 less transistor than NOR gate.

In my method NOR gate is more convenient because it has no transistors inside.

Are you a researcher in materials science or like solid state physics from electronics department?

 

[Merzifonlu]

Are you a researcher in materials science or like solid state physics from electronics department?

I am a mathematician. While studying neural networks, I realized that this is possible. With the help of a specialist of electronics friend of mine, me and he verified the idea on the board.

Indeed a NOR gate can be built without a transistor inside. If this is possible in the NOR gate, since we can build all gates with NOR gates, all of them can be produced by this method.

But insulating the logic gates becomes even more important.

P.S. I was researching neural networks to find very fast training algorithms. I couldn't find an algorithm as fast as I'd like but I found this idea.

 

[YeşilVatan]

I am a mathematician. While studying neural networks, I realized that this is possible. With the help of a specialist of electronics friend of mine, me and he verified the idea on the board.

Indeed a NOR gate can be built without a transistor inside. If this is possible in the NOR gate, since we can build all gates with NOR gates, all of them can be produced by this method.

But insulating the logic gates becomes even more important.

P.S. I was researching neural networks to find very fast training algorithms. I couldn't find an algorithm as fast as I'd like but I found this idea.

If it wouldn't be a hassle, can you do a quick summary of why this is important? I tried to google but my historian brain just had a meltdown from all the math stuff.

NUMBERS MASON WHAT DO THEY MEAN?

 

[uçuyorum]

If it wouldn't be a hassle, can you do a quick summary of why this is important? I tried to google but my historian brain just had a meltdown from all the math stuff.

NUMBERS MASON WHAT DO THEY MEAN?

Therr are billions of transistors on a chip nowadays and there was this Moore's law stating roughly every 2 years we would get twice as many on a silicon wafer of same size. However there are physical limits to how small it can get and as we get smaller you start seeing quantum stuff getting in the way. I read that possible smallest transistor takes 4 atoms. We are at 4nm wide transistors. A silicon atom is 0.21 nm wide. So we may not be able to get smaller. But if we don't need transistors to begin with we may have a lot more room for improvement, maybe.

 

[uçuyorum]

About logic circuits, NAND ( negation of and) and NOR( negation of or) gates can both be used solely to implement every logic circuit. We use NAND right now, and imagine you have a blank canvas of billions of these gates, then you print a circuit between these gates to make your desired logic circuits like for addition and multiplication. I'm not an expert on this but this should be it in a nutshell

 

[Merzifonlu]

But if we don't need transistors to begin with we may have a lot more room for improvement, maybe.

Exactly so, bravo!

The only thing that pisses me off right now is that the transistors are still needed for the digital buffer.

In my technique, there is no transistor inside the logic gate, but the gate must be well isolated. This makes it necessary to use a digital buffer.

Digital buffer - Wikipedia

en.wikipedia.org

About logic circuits, NAND ( negation of and) and NOR( negation of or) gates can both be used solely to implement every logic circuit. We use NAND right now, and imagine you have a blank canvas of billions of these gates, then you print a circuit between these gates to make your desired logic circuits like for addition and multiplication. I'm not an expert on this but this should be it in a nutshell

Yes, you are right.

Now think about it, there are no transistors inside the gates. There is no loss of (time & energy) caused by them.

And the best part is this: If you produce it with an unconventional method, you can get around the "intellectual rights minefield" whose chips were dropped by the USA!

 

[Huelague]

Exactly so, bravo!

The only thing that pisses me off right now is that the transistors are still needed for the digital buffer.

In my technique, there is no transistor inside the logic gate, but the gate must be well isolated. This makes it necessary to use a digital buffer.

Digital buffer - Wikipedia

en.wikipedia.org

Don’t forget to register patents.

 

[Yasar_TR]

Please share innovative up and coming new technologies all things related to Chip Manufacturing and developing techniques, in this thread.

 

[Passenger]

Samsung, SK Hynix test Chinese chip tools as hedge against US risks​

August 5, 202610:02 AM GMT+8Updated 14 hours ago


Summary

Korean memory-chip leaders test AMEC equipment at their China plants
Firms seek a contingency option if US curbs hit Western-tool servicing
Tests are not a commitment to deploy Chinese tools at scale
A win would give Chinese suppliers a major global customer endorsement
Companies deny testing AMEC equipment for use in China

Aug 5 (Reuters) - Samsung Electronics and SK Hynix are evaluating chipmaking equipment from China's Advanced Micro-Fabrication Equipment (AMEC) for possible use at their Chinese factories, three people familiar with the matter ‌said, as the South Korean firms hedge against the risk of tighter U.S. export controls.
The memory chipmakers began testing AMEC etching equipment about two years ago, when uncertainty was mounting over whether Washington would continue allowing them to import U.S. chipmaking tools into China, two of the sources said.

Samsung , said it has not tested AMEC equipment for use at its China factory and had not considered doing so.
SK Hynix , said it has not tested AMEC tools for use in China.
While the evaluations have yet to result in decisions on wider deployment, they offer the Shanghai-based company a rare chance to secure validation from some of the world's leading chipmakers.
More broadly, the trials underscore a paradox at the heart of U.S. ⁠technology controls: measures designed to constrain Beijing's semiconductor ambitions are creating opportunities for Chinese rivals to gain a foothold in foreign-owned fabs operating in China.


All sources declined to be identified due to the sensitivity of the matter.
AMEC and the Bureau of Industry and Security (BIS), which enforces the U.S. government's export controls, did not immediately respond to requests for comment.
TIGHTENING EXPORT CONTROLS
The U.S. Commerce Department designated Samsung and SK Hynix's Chinese factories as "validated end users" (VEU) in 2023, allowing imports of certain controlled U.S. equipment without obtaining individual licences.
Washington revoked the VEU authorization in 2025 and later granted an annual license to the chipmakers to bring in chip manufacturing equipment to their facilities in China for 2026.
Even so, both companies remain wary that future restrictions could extend beyond new equipment to the servicing, repair or replacement of Western tools already installed at their Chinese plants, the sources said.
As a result, the chipmakers are keeping Chinese suppliers in reserve as a potential way to maintain and upgrade existing production lines, rather than expand manufacturing capacity in China, the sources added.
Samsung operates its NAND flash memory chip plant in Xian, and SK Hynix has NAND facilities in ‌Dalian and ⁠a DRAM memory chip plant in Wuxi.
Their China factories rely heavily on etching tools supplied by U.S. firms including Applied Materials ,and Lam Research.
STAMP OF APPROVAL
For AMEC and China's emerging crop of semiconductor-equipment makers, winning approval from Samsung or SK Hynix would amount to a powerful commercial endorsement.
While Chinese equipment makers continue to trail overseas rivals in advanced lithography and some inspection systems, they have narrowed the gap in areas such as etching, deposition, cleaning and planarisation, often at significantly lower cost.


Chinese tools can cost 20% to 30% less than comparable equipment from established foreign suppliers, according to Dan Hutcheson, vice chair of research firm TechInsights.
AMEC ⁠equipment is already used by leading Chinese chipmakers, including NAND producer Yangtze Memory Technologies Co (YMTC), giving Samsung and SK Hynix greater confidence that some systems are mature enough for testing, the sources said.
The rise of Chinese suppliers could pose a longer-term challenge to dominant equipment makers including Applied Materials, Lam Research and KLA , as well as Japanese and European rivals that have long controlled key segments of the wafer-fabrication market.
China remains ⁠an important market for those companies. Applied Materials reported $8.53 billion in China revenue in fiscal 2025, equal to 30% of total sales.
Any breakthrough for Chinese suppliers would still face hurdles, including lengthy qualification processes, smaller service networks, intellectual-property concerns and potential political pressure from Washington.
It is also unclear whether Korean chipmakers would install Chinese equipment at domestic factories because of security and intellectual-property risks.
Yet ⁠U.S. export controls have helped create a fertile opening for China's equipment industry. Deutsche Bank estimates that Naura Technology , AMEC, Piotech and ACM Research will each generate more than $1 billion in revenue in 2026.
Together, they could capture 25% to 30% of China's projected $28 billion wafer-fabrication equipment market this year, the bank estimated. Excluding lithography and metrology, Chinese suppliers' share could approach 40%.
Reporting by Reuters staff; Additional reporting by Alexandra Alper in Washington, Hyunjoo Jin and Heekyong Yang in Seoul; Editing by Eduardo Baptista, Miyoung Kim and Shri Navaratnam

https://www.reuters.com/world/china/samsung-sk-hynix-test-chinese-chip-tools-hedge-against-us-risks-2026-08-05/